1. The Field of the Invention
The present invention relates to the processing of semiconductor substrates, such as silicon wafers, which are used in the manufacture of semiconductor devices. The present invention more specifically relates to the polishing or planarizing of the surfaces of semiconductor substrates using a process known as chemical mechanical planarization (CMP). Methods disclosed herein improve the result of CMP processes when performed on an apparatus known as a linear track polisher.
2. The Relevant Technology
In the fabrication of integrated circuits, numerous integrated circuits are typically constructed simultaneously on a single semiconductor substrate. To reduce the cost of producing individual semiconductor devices, it has long been an objective of semiconductor manufacturers to increase the number of devices on a single substrate. For a period of time this was accomplished primarily by a continual scaling down of the geometries of individual active devices within the integrated circuits. In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductor substrates described above. The term semiconductor substrate is contemplated to include such structures as silicon-on-insulator and silicon-on-sapphire.
Eventually, the scaling of active devices became less profitable as the limitations of the circuit speed and maximum functional density came to depend more on the characteristics of the electrical interconnects of the devices than on the scale of the devices themselves. In addition, the aspects of silicon utilization, chip costs, and ease of flexibility of integrated circuit design were also adversely affected by electrical interconnect technology restrictions. The approaches to lifting these limitations have involved the implementation of vertical stacking or integration of devices and their associated electrical interconnections, commonly referred to as multilevel interconnect (MLI) schemes. In MLI schemes, individual conductor layers are separated by dielectric layers which are sandwiched between the conductor layers. These dielectric layers are typically oxide or nitride layers which are grown or deposited on the substrate and are known as interlayer dielectrics (ILD).
One drawback of multilevel interconnection is a loss of topological planarity. Loss of planarity results in associated problems in photolithography and etch, as well as other problems. To alleviate these problems, the substrate is planarized at various points in the process to minimize non-planar topography and its adverse effects. As additional levels are added to multilevel interconnection schemes and circuit features are scaled to sub-micron dimensions, the required degree of planarization increases. Such planarization can be performed on either the conductor or the interlayer dielectric layers to remove high topography or to remove embedded particles.
The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates and selectivity between films of the semiconductor surface. This polishing process is often referred to as chemical mechanical planarization (CMP). The chemical slurry used in CMP contains abrasives therein to assist in the mechanical removal of the layer. When fixed abrasives are incorporated into a polishing pad in a CMP processed, abrasives are not needed in the chemical slurry.
CMP is implemented in dielectric layer planarization by growing or depositing an layer, such as oxide or nitride, on the semiconductor substrate, typically to fill in contact regions or trenches between metallization lines, and then removing the excess dielectric material using the CMP process, until a flat, smooth surface is achieved.
CMP processes have been used in the semiconductor industry for many years. A primary application of CMP processing has been the polishing of silicon substrates, such as silicon wafers, before active device fabrication. Only in recent years has the CMP process been applied to planarizing metallization layers and their inter-dielectric layers, and these new applications are the result of integrated circuit device fabrication processing scaling down to deep submicron geometries. A major hurdle to overcome in adapting CMP processes to the planarization of metallization and dielectric layers is that the typical thicknesses of the layers being planarized, and the variations in final thicknesses allowed over the entire surface area of the layers, are smaller than the critical dimensions associated with earlier semiconductor applications.
In addition to the need for tight tolerances in the planarizing of semiconductor metal and dielectric layers, there is a continuing need to reduce the amount of process time associated with the CMP material removal steps.
A type of apparatus known as a rotational polisher has been used widely in the practice of chemical mechanical planarization. The rotational polishing process involves holding and rotating a thin flat semiconductor substrate against a wetted polishing surface under controlled pressure and temperature. An example of such an apparatus is the Model 372 Polisher manufactured and distributed by IPEC Westech Systems, of San Jose, Calif.
FIG. 1 shows a rotational polisher 11 having a rotatable polishing platen 12, a substrate polishing head assembly 14 and a chemical supply system 18. Platen 12 is typically covered with a replaceable, relatively soft material 16 such as polyurethane.
Substrate polishing head assembly 14 holds semiconductor substrate 10 adjacent to platen 12. Substrate polishing head assembly 14 includes a motor (not shown) for rotating the polishing head and semiconductor substrate 10. Substrate polishing head assembly 14 further includes a polishing head displacement mechanism (not shown) which moves the substrate 10 back and forth across the platen 12 as it is rotating. Substrate polishing head assembly 14 applies a controlled downward pressure to semiconductor substrate 10 to hold semiconductor substrate 10 against rotating platen 12 so that a continuous polishing surface 34 on rotating platen 12 polishes semiconductor substrate 10. Chemical supply system 18 introduces a polishing slurry (not shown) to be used as an abrasive medium between platen 12 and semiconductor substrate 10.
Limitations of conventional rotational CMP polishing apparatus and processes are known to exist. It is necessary to have a constant material removal rate across the entire surface of the substrate, but the removal rate is related to the radial position of the substrate on the platen. The removal rate is increased as the semiconductor substrate is moved radially outward relative to the polishing platen due to higher platen rotational velocity. Additionally, removal rates tend to be higher at the edge of the substrate than at the center of the substrate because the edge of the substrate is rotating at a higher speed than the center of the substrate. FIG. 2 illustrates a perspective view, not to scale, of a topology having a typical thickness profile on a semiconductor substrate 10 which is an example of that which may be realized when planarizing a semiconductor substrate using rotational polisher 11 as described above.
Doped silicon dioxide layer materials known as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG) are used widely in the fabrication of semiconductor devices, and have been further used to provide a measure of surface planarity. Phosphorus-doped oxides are known to have numerous properties which are beneficial to the long term reliability of semiconductor devices, such as providing an improved barrier to moisture penetration, and acting as an effective trap for mobile ionic contaminants. In addition, BSG, PSG and BPSG materials have been used to achieve a measure of substrate surface planarity by depositing a BSG, PSG or BPSG layer on a substrate surface, then heating the substrate to flow the glass and planarize the layer. Such a technique is commonly referred to as reflow and has proven useful in the fabrication of semiconductor devices with relatively large geometries. BPSG films reduce reflow temperatures in such processes because boron plays a principal role in the lowering of glass viscosity.
Limitations to the use of BSG, PSG and BPSG reflow are known to exist, particularly when fabricating semiconductors which have relatively small device geometries or which have three or more dielectric/metal layers. The total thermal budget available to the reflow processes for such devices has to be minimized. Consequently, in order to produce the same degree of planarization obtained in higher temperature processes, the dopant concentration in the BPSG film must be further increased. When working with dimensions below 0.35 microns, however, higher doping levels of boron and phosphorus in the doped film fail to achieve the desired results, and CMP processes must be used on these layers in addition to reflow to fully planarize the substrate surface.
Planarization methods have been developed using a linear track polisher. An example of a linear track polisher is that which is manufactured by OnTrak Systems, Incorporated, of Milpitas, Calif. FIG. 3 shows an example of such an apparatus. Linear track polisher 30 includes a substrate polishing head assembly 32, a continuous belt having a continuous polishing surface 34 thereon, and a chemical mixture feed assembly 36.
A constant downward pressure is applied to the substrate polishing head assembly 32, holding a semiconductor substrate 10 against continuous polishing surface 34. Belt drive motors drive two belt drums 38 which cause continuous polishing surface 34 to move in the direction as indicated by arrows seen in FIG. 3. Continuous polishing surface 34 may consist of a polyurethane type material The chemical mixture feed assembly 36 delivers an aqueous mixture to the region where semiconductor substrate 10 makes contact with continuous polishing surface 34. The aqueous mixture is typically a colloidal slurry with abrasive characteristics suitable for the specific type of material being removed. In another embodiment, continuous polishing surface 34 may also contain fixed abrasives incorporated into a resin material. In the case of this other embodiment of continuous polishing surface 34, the aqueous mixture need not have abrasive characteristics.
The removal rate of material from the surface of the semiconductor substrate is determined by Preston""s relationship which derives a mechanical removal rate, RR:
RR=Kp*P*S;
where
P is the applied pressure;
S is the relative velocity between the substrate surface and the surface of the polishing pad or belt; and
Kp is the proportionality constant, or Preston""s coefficient, and is a function of temperature, slurry (pH, concentration, particle size), film properties, and polishing pad factors.
As seen in Preston""s relationship, by increasing the speed of continuous polishing surface 34 on the continuous belt of the linear track polisher, or by increasing the downward pressure on substrate polishing head assembly 32, the removal rate of material is increased proportionately.
Taking advantage of the Preston""s relationship, linear track polishers have the potential to achieve much higher material removal rates than rotational polishers, due to the high continuous belt speeds achievable, but limitations are known to exist. For instance, an increase in the removal rate, which can be achieved either by increasing the downward pressure or increasing the speed of continuous polishing surface 34, will also increase the probability that the material being removed from the surface of semiconductor substrate 10 will cause scratches or other surface defects as the surface material is being carried away, thereby damaging semiconductor substrate 10. Defects of this kind may cause electrical shorts between two conductive lines, improper optical scattering during subsequent patterning steps, or the non-adherence of subsequently deposited materials to the semiconductor substrate surface. Any of these or other similar problems caused by surface defects render the substrate unsuitable for further processing.
A further limitation exists for low or reduced viscosity layers, such as BSG, PSG or BPSG. The viscosity of these layers is reduced for increased dopant concentrations. The reduced viscosity of layers of this type can cause a glaze to accumulate on continuous polishing surface 34. The result of such glazing is a covering of the pores on continuous polishing surface 34, thereby inhibiting the ability of continuous polishing surface 34 to remove further material from the surface of semiconductor substrate 10. When this occurs, linear track polisher 30 must be stopped to recondition continuous polishing surface 34, thereby reducing the overall rate at which semiconductor substrates can be processed. A further effect of glazing is that the effective removal rate of the material from the surface of semiconductor substrate 10 can no longer be predicted by Preston""s relationship, thereby greatly reducing the ability to control the total amount of material removed during a planarization step.
While the linear track polisher has shown potential for improving the rate of material removal during a CMP operation on a semiconductor substrate, thereby improving the rate at which semiconductor substrate can be processed, advancements are needed to simplify the processing and improve the results obtained.
A novel method for the planarization of a semiconductor substrate is disclosed herein. The novel method is performed on a linear track polisher. The linear track polisher includes a substrate polishing head assembly in which the semiconductor substrate is affixed so that a front planar surface of the semiconductor substrate forms a polishing interface with a continuous polishing surface situated on a continuous belt. An aspect of the novel method is a routine for optimizing the speed for a selected time period at which the continuous polishing surface is moving so as to effect a maximum material removal rate from the front planar surface of the semiconductor substrate for a given pressure of the continuous polishing surface on the front planar surface of the semiconductor substrate.